Our technology
Four products. One thesis: you should own your security.
Silicon IP that makes fielded FPGAs quantum-safe and keeps host boot firmware encrypted at rest and on the wire — and a self-hosted AI platform that brings frontier-class engineering assistance inside the compliance boundary.
BootProtect
Patent-pending Errantry IP · with IC-SafetyToday's roots of trust are manufacturer-anchored: a vendor-fused key, checked by RSA/ECC hard logic that can't be patched. CNSA 2.0 puts National Security Systems on a 2030–2035 post-quantum timeline — and for fielded FPGAs, the only conventional path is replacing the silicon.
BootProtect re-creates the bitstream decryption key from the chip's own silicon fingerprint — nothing stored, nothing to extract, no asymmetric cryptography anywhere in the chain.
- Retrofit, not replace: reconfiguration alone, no recertification
- Post-quantum by construction: AES-256 + SHA2, zero asymmetric primitives
- Owner-controlled keys with in-field re-keying
- SiRF PUF independently assessed by Sandia National Laboratories
Manufacturer-anchored boot vs. BootProtect's owner-controlled, symmetric-only chain.
AES Crypto
Patent pendingEven strong cryptography leaks. Power-analysis attacks (SPA/DPA) recover secret keys by watching a chip's power draw. AES Crypto — the side-channel-hardened engine inside BootProtect, also available as standalone IP — makes those attacks see only noise.
- Dual AES cores in lock-step, exchanging valid and decoy data
- PUF-based TRNG injects fresh masking into every operation
- Same block, different power signature — every single run
- Drops in as a VHDL block on most FPGA families
Masked lock-step execution: an attacker never sees the same power signature twice.
Mithril
HAIR-compliant boot-flash root of trustA platform's earliest boot code lives in SPI flash outside the host's security perimeter — readable, copyable, and alterable with inexpensive bus-level tools before any software defense has begun to run. Native boot protections are fixed in host silicon and leave the image bare on the medium and on the wire.
Mithril sits transparently inline on the SPI path. The boot image stays encrypted at rest; Mithril decrypts it on-the-fly and re-encrypts everything returned to the host under keys bound to a live platform attestation — derived at run time, never stored. No change to the host, the flash device, or the boot software. To our knowledge, it is the only HAIR-compliant hardware root of trust in existence.
- Transparent inline insertion — the host sees a standard SPI flash
- Attestation-bound AES-256-GCM, at rest and in transit; no static secret to recover
- Proven on hardware: an Intel Ice Lake-D host boots through Mithril inline
- Vendor-portable FPGA logic — Microchip and Lattice today, AMD/Xilinx and Altera underway
- Post-quantum upgrade path through BootProtect
The host completes bootstrap discovery and loads its full boot image through Mithril — captured end to end on RAE's bit-accurate SPI instrument.
Reg
Self-hosted · CUI/ITAR-safe · U.S.-origin modelsCommercial AI assistants process every prompt in a vendor cloud — disqualifying for CUI and ITAR work. Reg inverts the trust model: the data stays put, and the models come to it.
Air-gapped on hardware you own, Reg is a full engineering copilot — chat, documents, mail and calendar with human-approval gates — plus a verified FPGA/VHDL toolchain no other AI system offers.
- No prompt, document, or design ever leaves your boundary
- U.S.-origin models only — no PRC-origin weights, even air-gapped
- Verified VHDL: only code that passes simulation ships
- FPGA sign-off across Microchip, Lattice, AMD/Xilinx, Altera
- In production today — Reg runs RAE's own engineering
Reg's System Designer with a real PolarFire design open — top-level blocks, I/O pin assignment, one-click Build & Verify, and an "Ask Reg" prompt to change the design in plain language. (click to enlarge)
Drilling into a single block of the same design: the full wired netlist, one level down. (click to enlarge)
